Anti-fuse devices permit connecting underlying semiconductor devices otherwise isolated by rupturing, or converting to a lower resistance layer, an overlying fusing element by a high voltage electrical pulse. This permits connection of the underlying semiconductor device(s) with a predetermined circuit within the integrated circuit chip through a wire line overlying the fusing element. Anti-fuse modules may be used, for example, to compensate for defective devices elsewhere on the chip discovered during testing of the chip (wafer sort) by permitting access to underlying back-up semiconductor devices.
For example, field-programmable gate arrays, (FPGA) have been designed to contain the needed row of arrays, as well as additional rows of spare arrays, accessed if needed to replace ineffective counterparts, or to modify a specific design. These additional or spare arrays, or one-time fusible link structures, are sometimes comprised of an antifuse based programmable interconnect structure. The structure consists of an antifuse layer, usually a thin dielectric layer, placed between electrodes or conductive materials. When needed this antifuse material can be ruptured, or converted to a lower resistance layer, via a high voltage electrical pulse, resulting in creation of the replacement array structure.
Anti-fuse modules are fabricated along with other devices on the semiconductor chip. A prior art method of fabricating an anti-fuse module along with a normal device, such as a copper (Cu) dual damascene interconnect, required etching the antifuse stack over the normal device area which could damage the via portion of the normal device.
U.S. Pat. No. 5,877,075 to Dai, Jr. et al. describes a method of forming a dual damascene pattern employing a single photoresist layer.
U.S. Pat. No. 5,741,26 to Jain et al. describes a method for forming a dual damascene structure using an anti-reflective coating (ARC) layer of dielectric tantalum nitride (Ta.sub.3 N.sub.5) to reduce the amount of reflectance from the underlying conductive region and thus reduce the distortion of the photoresist pattern.
U.S. Pat. Nos. 5,705,849 and 5,602,053, both to Zheng et al. describe an anti-fuse structure and the method of making it, respectively. The anti-fuse structure comprises two dual damascene connectors separated by a structure comprising a pair of alternating layers of silicon nitride and amorphous silicon.